The design and manufacture of very large scale integration (VLSI) integrated circuit devices continue to become more complex and sophisticated. Current VLSI technology allows for the design and manufacture of large-area integrated circuits with sub-micron feature sizes, such that millions of devices can be placed on a single chip. Even using the highest level of control in state-of-the-art technology, a fabrication process only provides control of transistor characteristics to a given range, generally a Gaussian distribution, and is not able to provide precise control to specific characteristic values. Such process gradients occur not only within a single batch of wafers, but exhibit themselves across a single wafer as well. VLSI design libraries typically are characterized using the extremes of the process distribution, referred to in the industry as the “slow” and “fast” process corners. A “typical” process corner corresponding to the center of the process distribution is also often provided.
Ideally, it would be desirable to know the process corner for each individual die on a wafer. Since it is currently impractical to obtain such knowledge in large-scale device manufacture, VLSI design addresses the worst operating conditions, or slow process corner. By choosing a design for the slow process corner, circuit designers can be sure that the typical and fast process corners will still work with that single design. If the designers were to choose a design that was optimal for typical or fast process corners, then those die corresponding to slow process corners might not operate properly, resulting in lower yields and higher cost per device.
A downside to this approach, however, is that all die then operate as if they are from the slow process corner. If a particular die is not at the worst process corner, then the chip likely is operating at a lower frequency than is otherwise possible. Increasing the frequency would result in improving chip performance. The chip also may be operating at a higher voltage than is necessary to meet timing requirements, which results in unnecessary power usage. Unnecessary power usage is becoming an important issue as IC chips are increasingly used in portable devices that run from battery power.
Today, there are means available to adaptively adjust the operating needs of a chip regardless of the process corner of that chip. In one such process, an advanced process power controller is used to detect a slack in critical timing. If the critical path timing has not reached a maximum, the voltage can be lowered to provide power savings. This closed loop method requires characterization collaterals to make the approach work. Therefore, a simpler process that quickly and cheaply provides process corner information is desired.
Above-referenced related U.S. application Ser. No. 11/272,928 discloses process corner estimation circuit embodiments and methods that overcome deficiencies in conventional chip designing, testing and manufacturing processes by providing for simple determination of process corner information on a die-to-die basis. By determining the process corner of each die, such as a fast, typical or slow process corner, as discussed above, the performance of each die can be improved where possible, such as by running the die at a lower voltage or at a higher frequency.
It is well known that the delay of a standard integrated circuit is typically determined by the supply voltage, temperature and process corner of the circuit. As discussed in above-referenced application Ser. No. 11/272,928, if two of the variables (e.g., supply voltage and temperature) are fixed, then the remaining variable (process corner) can dictate the delay of a circuit. A digital code can be produced that represents the process corner on which a particular die falls, without the need for tedious bench measurements or other complicated procedures.
Referring to FIG. 1, application Ser. No. 11/272,928 discloses a circuit 100 that can be included on each individual die formed on a semiconductor wafer in order to provide an estimate of process corner information. The circuit 100 includes a clock generator circuit 102 for generating a timing signal. The clock generator circuit 102 is a free-running clock that can be started through application of a trigger voltage. The output frequency of a timing signal from the clock generator is directly proportional to the supply voltage (VDDL) and temperature. By applying a lower supply voltage, such as a voltage of about 0.6V for the exemplary 1.8V process, the frequency of the timing signal will be lower, such that the delay of each standard cell becomes “worse” and the period of the output (a quasi-square wave for a digital clock generator) is increased. As the period of the timing signal increases, the timing differences between the extreme process corners become accentuated. The period/frequency of the clock generator 102 at a particular voltage and a particular temperature then can be a good indication of the process corner for that particular die.
FIG. 2 shows period vs. voltage plots, at room temperature for a 0.18 μm process, for three different die, representing a slow process corner 200, a typical process corner 202 and a fast process corner 204. As can be seen, there is less separation between periods of the process corners at higher supply voltages (around 1.0V) than at lower supply voltages (around 0.6V). At higher voltages, such as at the 1.8V normal operating voltage, it would be difficult to make a distinction between process corners. A very high resolution process would be needed.
With reference to the FIG. 1 circuit 100, if the clock generator 102 can be run at 0.6V, for example, the separation between process corners is much more distinct. In this example, a slow process corner has a period of about 180 ns, while a typical process corner has a period of about 80 ns and a fast process corner has a period of about 30 ns. This large separation makes it easy to determine the process corner of a die.
The corner indicator circuit 100 shown in FIG. 1 can also measure the output timing of the clock generator circuit 102. Since the clock generator 102 is operating at a relatively low voltage, the output of the clock generator 102 can be passed through a level shifter 104. The level shifter 104 shifts the voltage level of the timing signal from the input level, 0.6V in this example, to the output level needed for the device counter, 1.8V in this example. As can be seen, the level shifter 104 takes as input both a low supply voltage (VDDL) and a high supply voltage (VDDH). The level shifted timing signal can be input into any appropriate counting device capable of measuring the period/frequency of the adjusted timing signal and generating an output signal in response thereto. In the FIG. 1 circuit 100, an output code logic block 106 includes a slow clock counter 108 and a fast clock counter 110. The slow clock counter 108 in this embodiment receives as input the high supply voltage (VDDH), the trigger/reset/enable signal (enb), and the level shifted timing signal received from the level shifter 104. The slow clock counter 108 counts a number of cycles, such as 10 cycles, of the level shifted timing signal. For a slow process corner at room temperature with a 0.6V supply voltage, the period of the timing signal should be about 180 ns, as discussed above with respect to FIG. 2. After counting 10 cycles (corresponding to 1800 ns), or the selected number of cycles to be counted, the slow clock counter 108 can generate a flag, or hold signal. This hold signal can be input into the fast clock counter 110.
The fast clock counter 110 receives as input the same trigger signal (enb) that is supplied to the clock generator 102 and the slow clock counter 108. The fast clock counter 110 also receives a fast clock signal, in this example shown to be a 100 MHz clock signal. While the slow counter 108 counts the (level adjusted) output pulses from the clock generator 102, the fast clock counter 110 counts based on the 100 MHz fast clock signal (clk_in). In this example, each clocked cycle will take 10 ns. As discussed above, the slow clock counter 108 outputs a hold signal after 10 cycles of the timing signal, or after about 1800 ns. This hold signal is input to the fast clock counter 110, which will be caused to also stop at about 1800 ns after the trigger signal. Since the fast clock counter 110 is running at 10 ns/cycle, the fast clock counter 110 will generate a count of 180 cycles. This value (180) corresponds to the period of the timing signal output from the clock generator 102 for this particular die, and is a digital count of the period without the need for a frequency counter or any other element.
The clock signal selected (here 100 MHz) can be based on a simple relationship, such that the cycle count (pd_out) output by the fast clock counter 110 corresponds to the period of the timing signal. The period of the fast clock signal can be set to an integer value, such as 10 ns, that corresponds to the number of counts, again 10, recorded by the slow clock counter 108. If the slow clock counter 108 is set to count 20 cycles of the timing signal, the period of the fast clock signal can be set to 20 ns (50 MHz). By matching the period of the fast clock signal to the number of counts of the slow clock counter 108, the output of the fast clock counter 110 can correspond to the period of the timing signal, which can provide an immediate indication of the process corner for the die by identifying that value on the plot of FIG. 2. It should be understood that the output signal can be input to any circuit or device capable of receiving this signal and generating a signal in response thereto that is an indication of the process corner of that die. This indication can be used to adjust the operating conditions of the die, such that the die can be run at a faster speed or at a lower voltage where appropriate.
In the above-cited application Ser. No. 11/272,928, the process information can be estimated by operating the circuit at a fixed voltage at a particular temperature. This implies that the determination must be performed prior to use of the circuit in its normal application, such as at test. The result is then stored in a non-volatile memory (or by some other conventional method). During normal circuit operation, the stored result is retrieved to determine the process corner in which the circuit actually lies. This is required because three variables (supply, temperature, process corner) affect the result for the circuit and temperature at the time of normal operation may not be known.
As discussed above, FIG. 2 shows the characteristics of the circuit at room temperature versus supply voltage. Depending upon the process corner, the result at, for example, 0.6V is very distinct among the extreme (slow and fast) process corners and the typical process corner. FIG. 3, however, shows that, for different temperatures, the result at the 0.6V of one process corner overlaps the result of another process corner for a different temperature. The result, for example, for slow process corner at “hot” can be interpreted as the result typical process corner at “cold.” It is to be noted that, at low voltage operation (when the gate-source voltage of a transistor is comparable to the threshold voltage), the transistor delay has an inverse relationship with temperature; that is, as temperature increases, the delay is reduced. This is opposite to the typical characteristics at regular operating voltage, such as at 1.8V for the example process used in this description. This behavior is observed in that the clock period (which is dependent upon delay) is higher at “cold” that at “hot” temperature.
As discussed in greater detail below, the present invention provides a circuit that enables the determination of process corner information without the need to store the result by providing an integrated temperature compensation scheme. The temperature compensation scheme ensures that the result from the circuit is independent of temperature.